Design of a Low-area Digit Recognition Accelerator Using MNIST Database

Joonyub Kwon - Department of Semiconductor System Engineering, Sangmyung University, 31, Sangmyeongdae-gil, Dongnam-gu, Cheonan-si, Chungcheongnam-do, 31066, Republic of Korea
Sunhee Kim - Department of Semiconductor System Engineering, Sangmyung University, 31, Sangmyeongdae-gil, Dongnam-gu, Cheonan-si, Chungcheongnam-do, 31066, Republic of Korea

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Deep neural networks, which is a field of artificial intelligence, have been used in various fields. Deep learning is processed on high-performance GPUs or TPUs. It requires high cost as much as its good performance. Recently, as the demand for edge computing increases, many studies have been conducted to perform complex deep learning operations in a low-computing processor. Among them, a typical study is to lighten the deep learning network. In this paper, we propose a handwritten digit recognition hardware accelerator suitable for edge computing using MNIST database. After setting the correction rate for MNIST to 94% and performing network lighting processes, a hardware structure that can reduce the area of hardware and minimize memory access is proposed. Basically, the network is set as a two-layer fully connected network. The network is modeled with Python and lighten while checking the performance. Network parameters, weighs and biases, are quantized. The pixel number and bit number of MNIST input data are also reduced. The number of MAC units and the processing order of the hardware accelerator are determined so that there is no not used MACs while performing the MAC operations in parallel. It is designed with Verilog HDL and its functions are checked in Modelsim. And then it is implemented in Xilinx Zynq ZC-702 to verify the operations. The designed number recognition accelerator is expected to be widely used in edge devices by reducing the area and memory access.


MNIST; accelerator; digit recognition; edge computing; fully-connected network.

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